
# PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator

create_project -name jrmoc_cmos -dir "D:/Test/jrmoc_cmos/prj/planAhead_run_1" -part xc6slx45csg324-3
set_param project.pinAheadLayout yes
set srcset [get_property srcset [current_run -impl]]
set_property target_constrs_file "jrmoc_cmos.ucf" [current_fileset -constrset]
set hdlfile [add_files [list {../src/ip/ddr_ctrl/mcb_controller/iodrp_mcb_controller.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../src/ip/ddr_ctrl/mcb_controller/iodrp_controller.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../src/ip/ddr_ctrl/mcb_controller/mcb_soft_calibration.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../src/ip/ddr_ctrl/mcb_controller/mcb_soft_calibration_top.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../src/ip/ddr_ctrl/mcb_controller/mcb_raw_wrapper.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../src/ip/FIFO/SCFIFO_128x8_FWFT.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
add_files [list {../src/ip/FIFO/SCFIFO_128x8_FWFT.ngc}]
set hdlfile [add_files [list {../src/ip/ddr_ctrl/mcb_controller/mcb_ui_top.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../src/lcd_rgb_buff.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../src/lcd_gray_buff.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../src/ip/RAM/BRAM_320X240B.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
add_files [list {../src/ip/RAM/BRAM_320X240B.ngc}]
set hdlfile [add_files [list {../src/ip/FIFO/SCFIFO_256X32D.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
add_files [list {../src/ip/FIFO/SCFIFO_256X32D.ngc}]
set hdlfile [add_files [list {../src/ip/FIFO/FIFO_32x512_B.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
add_files [list {../src/ip/FIFO/FIFO_32x512_B.ngc}]
set hdlfile [add_files [list {../src/ip/FIFO/FIFO_16x1024_B.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
add_files [list {../src/ip/FIFO/FIFO_16x1024_B.ngc}]
set hdlfile [add_files [list {../src/ip/FIFO/DCFIFO_2048_8I32O_BRAM.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
add_files [list {../src/ip/FIFO/DCFIFO_2048_8I32O_BRAM.ngc}]
set hdlfile [add_files [list {../src/ip/ddr_ctrl/memc_wrapper.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../src/ip/ddr_ctrl/infrastructure.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../src/lcd_ctrl.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../src/ip/ddr_ctrl/ddr_ctrl.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../src/cmos_intf.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../src/arm_ebi.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../src/jrmoc_cmos.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set_property top jrmoc_cmos $srcset
add_files [list {jrmoc_cmos.ucf}] -fileset [get_property constrset [current_run]]
open_rtl_design -part xc6slx45csg324-3
